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|4/26/2005 3:52 AM|
1.) how do i set the clock frequency for a time
based effect like a flanger or delay?
2.) Is the Capacitor the clock frequency?
3.) what does the clock do ?
|4/26/2005 12:41 PM|
Go to the Synth DIY site (http://www.synthdiy.com/view/filecat.asp), or try to locate the datasheet for the MN3101 or MN3102 (like here: http://wwww.ges.cz/sheet/m/mn3101.pdf). This will explain the role that the cap plays. Th datasheets at synthdiy will explain an enormous amount.
What does the clock "do"?
When it comes to BBDs, the clock activates the teeny tiny FET-based switches in the chip so that all the "analog samples" the chip has stored are shifted over one stage. One clock cycle permits the little capacitors to charge up with whatever is at their input (and that could be the content/charge of the previous stage or the input tot he chip itself). The last stage becomes the output of the chip, and the first stage acquires another sample.
The higher the clock frequency, the faster that movement across stages occurs, which means the less time it takes for a sample acquired in stage 1 to suddenly find itself being booted out of the last stage. Faster clock equals less time delay. Keep the clock the same, but add more stages, and you increase the time delay. A chip with more stages but clocked faster is capable of producing less time delay than one with fewer stages but clocked at a much slower rate.
Though the cap is but one component of setting the rate/frequency of the clock chip, it is an easy thing to identify and change with predictable results. Open up just about any under-$200 analog chorus or flanger, and you will see either an MN3101, MN3102, CD4046 or CD4047 chip being used for the clock. You will also likely see a capacitor of less than 1000pf (and usually less than 500pf) huddled up against the clock chip. It will probably be the only one of that value range nearby. While it MAY be possible to also change the value of a 100k resistor and alter the clock frequency, that cap is far more easily located than the resistor. Change that cap for another value and you're in business. The change in delay-time range will be proportinal to the change in cap value. So, if the cap used to be 220pf, and the delay range was from 4-20ms, replacing that cap with 110pf (1/2 the previous value) will change the delay range to 2-10ms. That change in delay range will be true whether it is the passive components tied to the clock alone which set delay time, or whether the clock is being modulated by a low frequency oscillator to make the delay time sweep up and down.
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|4/26/2005 2:36 PM|
Thanks Mark Hammer for the information
1.) I thought the clock was used to just control
the on/off times of the tiny FET based switches
in the BBD chip so the tiny capacitors have
a on/off stotage passing from discharging to
another capacitor next to it and charging when
the clock is set high the FET is turned on and
charges the capacitor when the clock is set low
the FET is turned off and the capacitor
discharges. And the Delay is the charging and
discharging from one capacitor to another?
2.) The Clock has 2 lines that are out of phase
to hook up to the BBD to turn the FETs on?
Why 2 does the Clock has 2 output lines?
3.) What is the Clock output is it voltage or
4.) The LFO is hooked up to the Clock what does
it do to the Clock?
5.) The Lfo is outputing voltage to the clock
does it modulate the Clock?
does it modulate the Clocks frequency?
|4/26/2005 6:50 PM|
The "clock" is essentially a voltage controlled oscillator. The voltage controlling its frequency can either come from an arrangement of a few passive components on the chip itself, or from some external voltage applied to the appropriate input point on the clock chip. This is no different than controling something like a 555 timer chip with a few passive components or feeding it am external voltage to change its frequency.
Think about BBDs the way a set of locks on a canal works. To allow a boat to go from one level to another, the locks provide several compartments. Let's say two in this example. The boat comes along the canal, and the first set of doors opens up, letting the boat in the first compartment. The other 2 sets of doors remain closed/sealed. The first set of doors close and the compartment either fills up (if the intent is to raise the level of the boat) or drains out (if the intent is to lower the boat to another level). Once the desired level is reached, the next set of doors is opened and the boat moves into the NEXT compartment, at which point the door is once again closed. The water level in that compartment is then adjusted so that it matches the water level outside the compartment in the canal. When the boat is at the same water level as the next part of the canal, the third set of doors are opened and the boat goes merrily on its way.
So, how does this apply to BBDs? The storage elements in the BBD are little capacitors. To move the charge from one capacitor/storage-element to another, a kind of electronic doorway has to open up. That "doorway" is a FET. Like the lock compartment, though, you can't open up the doorway to the NEXT station/compartment, unless you first close the doorway from the *previous* station/compartment, or else all the charges, like all the water, would just blend together.
So, what happens with BBDs is that that there are two sets of interpolated doorways, controlled by alternate clock pulses. On pulse N, whatever is in caps 1, 3, 5, 7, 9, etc, is "allowed" to drain into stages 2, 4, 6, 8, 10, etc. Since 1, 3, 5, 7, 9, no longer "have anything", the door between 1 and 2, 3 and 4, etc., is closed, and the front door to THOSE sections now opens up in response to pulse N+1 and they fill up.
This is why there are two clock pins on the BBD and why the MN3101 and 3102 put out two complementary clock pulses. It is also why BBDs almost always have two outputs that are ixed together. Each set of FET/cap cells contains essentially HALF of the audio signal (actual every alternate sample). To reconstitute the original, these two sets of samples have to be merged. The fact that the two sets of storage elements are stepped along by the SAME clock chip means their entry and exit from the chip will be orderly and coordinated. Put another way, if you tried to drive ONE bbd with two separate unsynced clock sources, the BBD output would be unrecognizable.
The sole exception to this in either the Matsushita and Reticon chips was the 8-pin SAD512. This chip was designed to take a single clock pulse and do the conversion to a pair of alternating clock pulses internally. Perhaps some of the Philips chips generally only available in Europe did this. I am however less familiar with them.
|4/26/2005 11:41 PM|
||clock 101 service manual|
hi thanks Mark Hammer
1.) How do i test with my oscilloscope the
output of a LFO DC and AC voltages?
a.) What Wavefrom Checking should i Do?
b.) What Voltage should i be looking
for DC and AC wise?
in ball park general
c.) How Measure the frequency of the LFO?
What Frequecy should i be measuring?
2.) How to test the clocks output?
a.) What should i be looking for on the
output of the clock with my Oscilloscope?
1.) Waveform clock output Checking?
2.) Is it pulses?
3.) Whats the Duty cycle of the pulses?
b.) How do i check the Frequency of the
clock with my Oscilloscope or
3.) How to measure Clock frequency VS Delay Time?
|4/27/2005 2:38 PM|
The datasheets for the MN3101 and 3102 probably explain this better than I could.
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